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irs21952spbf features ? 2 low side output channels sharing common ground ? 1 high side output channel ? cmos schmitt trigger inputs with pull down resistor ? under voltage lockout on all channels ? 5 v compatible logic level inputs ? immune to ?vs spike and tole rant to dvs/dt & dvss/dt ? shoot through prevention logic descriptions high side & dual low side driver ic product summary v offset (low side) -600 v (vss) v offset (high side) 600 v (com) v out 10 v to 20 v t on /t off (typ) 330 ns/330 ns i o+/- 0.5 a/0.5 a package 16-lead soic (narrow body ) typical connection diagram the irs21952 contains 2 low side outputs sharing common ground and 1 high side output. low side drivers can tolerate up to -600 v below input signal (vss: input supply return). high side driver can tolerate up to 600 v above low side ground (com: low side supply return). the irs21952 has better propagation delay and thermal characteristics compared to a photo-coupler driver. the logic inputs are compatible with standard cmos or lsttl output. proprietary hvic and latch-up immune cmos technologies enable ruggedized monolithic construction.
irs21952spbf 2 absolute maximum ratings absolute maximum ratings indicate sustained limits bey ond which damage to the device may occur. all voltage parameters are absolute volt ages referenced to com. symbol definition min max units hin lin1 lin2 floating logic level input voltage vss-0.3 vdd+0.3 vdd floating logic input supply voltage -0.3 625 vss floating logic input supply return voltage vdd-25 vdd+0.3 vb high side floating well supply voltage -0.3 625 vs high side floating well supply return voltage vb-25 vb+0.3 ho high side floating gate driv e output voltage vs-0.3 vb+0.3 vcc low side supply voltage -0.3 25 lo1 lo2 low side output voltage -0.3 vcc+0.3 v dvs/dt allowable vs offset transient relative to earth ground - 50 v/ns dvss/dt allowable vss offset transient relative to earth ground - 50 v/ns p d package power dissipation @ t a <=+25 oc - 1 w r ja thermal resistance, junction to ambient - 100 oc/w t j junction temperature -55 150 oc t s storage temperature -55 150 oc t l lead temperature (soldering, 10 seconds) - 300 oc recommended operating conditions for proper operation, the devic e should be used within the recommended conditi ons. all voltage param eters are absolute voltages referenced to com. symbol definition min max units hin lin1 lin2 floating logic level input voltage vss vdd vdd floating logic input supply voltage vss+4.5 vss+5.5 vss floating logic input supply return voltage -5 600 vb high side floating well supply voltage vs+10 vs+20 vs high side floating well supply return voltage -5 600 ho high side floating gate drive output voltage vs vb vcc low side supply voltage 10 20 lo1 lo2 low side output voltage 0 vcc v t a ambient temperature -40 125 oc note 1: logic operation for v s of ?5 v to 600 v. logic state held for v s of ?5 v to ?v bs . (please refer to design tip dt97-3 for more details).
irs21952spbf 3 static electrical characteristics (vb-vs)=15 v. the v in , v in,th , v bsuv , v o , i o and i in parameters are referenced to v s . t a = 25 o c unless otherwise specified. symbol definition min typ max units test conditions v ccuv + v cc supply undervoltage positive going threshold 7.5 8.6 9.7 v ccuv - v cc supply undervoltage negative going threshold 7.0 8.2 9.4 v bsuv+ v bs supply undervoltage positive going threshold 7.5 8.6 9.7 v bsuv- v bs supply undervoltage negative going threshold 7.0 8.2 9.4 v dduv+ v dd supply undervoltage positive going threshold 3.3 4.1 4.9 v dduv- v dd supply undervoltage negative going threshold 2.9 3.7 4.5 v i lkvcc i lkvbs offset supply leakage current ? both input well and output well --- --- 50 v b = v s = 600 v v cc = v com = 600 v i qbs quiescent v bs supply current --- 70 140 i qdd quiescent v dd supply current --- 140 280 i qcc quiescent v cc supply current --- 200 400 a vin = 0 v or 5 v v ih logic ?1? input voltage 3.5 --- --- v il logic ?0? input voltage --- --- 0.6 v oh high level output voltage, v bias -v o --- --- 0.1 i o = 0 a v ol low level output voltage, v o --- --- 0.1 v i o = 0 a i in+ logic ?1? input bias current --- 2 10 vin = 5 v i in- logic ?0? input bias current --- --- 5 a vin = 0 v i o+ output high short circuit pulsed current --- 0.5 --- v o =0 v,v in =0 v, pw<=10 s i o- output low short circuit pulsed current --- 0.5 --- a v o =15 v,v in =5 v, pw<=10 s
irs21952spbf 4 dynamic electrical characteristi cs (all values are target data) (vb-vs)= 15 v. c l = 1000 pf unless otherwise specified. a ll parameters are reference to com. t a = 25 o c unless otherwise specified. s y mbol definition min t yp max units test conditions t on turn-on propagation delay of high and low side --- 330 --- v ss =200 v, v s =0 v t off turn-off propagation delay of high and low side --- 330 --- v ss =200 v, v s =400 v t r turn-on rise time of high and low side --- 25 70 v ss =200 v, v s =0 v t f turn-off fall time of high and low side --- 25 70 v ss =200 v, v s =400 v mt_on turn on propagation delay matching --- --- 50 v ss =200 v, v s =0 v mt_off turn off propagation delay matching --- --- 50 ns v ss =200 v, v s =400 v
irs21952spbf 5 functional block diagram level shift up r r q s uvlo pulse filter level shift down vdd lin2 lin1 hin ho vb vs vss r r q s uvlo pulse filter vcc lo2 com r q r s uvlo pulse filter lo1 shoot through prevention logic uvlo
irs21952spbf 6 lead definitions symbol description vdd input logic supply voltage hin logic input for high side gate driver lin1, lin2 logic inputs for low side gate driver vss input logic supply return lo1, lo2 low side outputs vcc low side supply voltage com low side supply return ho high side output vb high side floating supply voltage vs high side floating supply return lead assignments
irs21952spbf 7 figure 1: switching time waveforms shoot through prevention logic hin1 lin1 lin2 ho1 lo1 lo2 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0
irs21952spbf 8 0 100 200 300 400 500 600 700 800 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on delay time (ns) figure 2a. turn-on time vs. tem p erature ty p. 0 100 200 300 400 500 600 700 800 10 12 14 16 18 20 v bias supply voltage (v) turn-on delay time (ns) figure 2b. turn-on time vs. supply voltage typ. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off time (ns) figure 3a. turn-off time vs. tem perature t yp . 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) turn-off time (ns) figure 3b. turn-off time vs. supply voltage ty p. 0 20 40 60 80 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-on rise time (ns) fiure 4a. turn-on rise time vs.tem p erature ty p. 0 20 40 60 80 10 12 14 16 18 20 v bias supply voltage (v) turn-on rise time (ns) figure 4b. turn-on rise time vs. su pp l y volta g e t yp .
irs21952spbf 9 0 20 40 60 80 -50 -25 0 25 50 75 100 125 temperature ( o c) turn-off fall time (ns) figure 5a. turn-off fall time vs. tem p erature t yp . 0 20 40 60 80 10 12 14 16 18 20 v bias supply voltage (v) turn-off fall time (ns) figure 5b. turn-off fall time vs. supply voltage ty p. 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 temperature ( o c) input voltage (v ) figure 6a. logic "1" input voltage vs. tem perature mi n. 1 2 3 4 5 6 10 12 14 16 18 20 vcc supply voltage (v) input voltage (v ) figure 6b. logic "1" input voltage vs. supply voltage min. 0 1 2 3 4 -50 -25 0 25 50 75 100 125 temperature ( o c) input voltage (v ) figure 7a. logic "0" input voltage vs. tem perature max. 0 1 2 3 4 10 12 14 16 18 20 v cc supply voltage (v) input voltage (v ) figure 7b. logic "0" input voltage vs. supply voltage max
irs21952spbf 10 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature ( o c) high level output voltage (v ) figure 8a. high level output vs. tem perature max. 0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 v cc supply voltage (v) high level output voltage (v ) figure 8b. high level output vs. supply voltage max. 0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature ( o c) low level output voltage (v) figure 9a. low level output vs.temperature max. 0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 v cc supply voltage (v) low level output voltage (v) figure 9b. low level output vs. supply voltage max. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) offset supply leakage current (ua ) max. figure 10a. offset supply leakage current vs. tem perature 0 100 200 300 400 500 0 100 200 300 400 500 600 v b boost voltage (v) offset supply leakage current (ua ) max. figure 10b. offset supply leakage current vs. supply voltage
irs21952spbf 11 0 100 200 300 400 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs supply current (ua) figure 11a. v bs supply cur re nt vs. tem perature ty p. max. 0 100 200 300 400 10 12 14 16 18 20 v bs supply voltage (v) v bs supply current (ua) figure 11b. v bs supply cur re nt vs. supply voltage ty p. max. 0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc supply current (ua) figure 12a. v cc supply cur re nt vs. temperature max. t yp . 0 200 400 600 800 1000 10 12 14 16 18 20 v cc supply voltage (v) v cc supply current (ua) figur e 12b. v cc supply cur re nt vs. supply voltage max. ty p. 0 100 200 300 400 500 600 -50 -25 0 25 50 75 100 125 temperature ( o c) v dd supply current (ua) figure 13a. v dd supply curre nt vs. tem perature max. t yp . 0 100 200 300 400 500 600 10 12 14 16 18 20 v dd supply voltage (v) v dd supply current (ua) figure 13b. v dd supply cur re nt vs. supply voltage max. ty p.
irs21952spbf 12 0 10 20 30 40 -50 -25 0 25 50 75 100 125 temperature ( o c) logic "1" input current (ua ) figure 14a. logic "1" input current vs. tem perature max. ty p. 0 10 20 30 40 10 12 14 16 18 20 v cc supply voltage (v) logic "1" input current (ua ) figure 14b. logic "1" input current vs. supply voltage max. ty p. 0 2 4 6 8 10 -50 -25 0 25 50 75 100 125 temperature ( o c) logic "0" input current (ua ) figure 15a. logic "0" input current vs. tem perature max. 0 2 4 6 8 10 10 12 14 16 18 20 v cc supply voltage (v) logic "0" input current (ua ) figure 15b. logic "0" input current vs. supply voltage max.
irs21952spbf 13 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc uvlo threshold (+) (v) figure 16. vcc undervoltage threshold (+) vs. tem perature ma x. typ. mi n . 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v cc uvlo threshold (-) (v) figure 17. v cc undervoltage threshold (-) vs. tem p erature max ty p. min. 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs uvlo threshold (+) (v) figure 18. v bs undervoltage threshold (+) vs. tem perature max. ty p. min. 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v bs uvlo threshold (-) (v) figure 19. v bs undervoltage threshold (-) vs. tem p erature max ty p. min. 1.00 2.00 3.00 4.00 5.00 6.00 7.00 -50 -25 0 25 50 75 100 125 temperature ( o c) v dd uvlo threshold (+) (v) figure 20. v dd undervoltage threshold (+) vs. tem perature max. ty p. min. 1 2 3 4 5 6 7 -50 -25 0 25 50 75 100 125 temperature ( o c) v dd uvlo threshold (-) (v) figure 21. v dd undervoltage threshold (-) vs. tem p erature max. t yp . min.
irs21952spbf 14 0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) output source current (ua ) figure 22a. output source current vs. temperature ty p. 0 200 400 600 800 1000 10 12 14 16 18 20 v bias supply voltage (v) output source current (ua ) figure 22b. output source current vs. supply voltage ty p. 0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) output sink current (ua ) figure 23a. output sink current vs.temperature ty p 0 200 400 600 800 1000 10 12 14 16 18 20 v bias supply voltage (v) output sink current (ua ) figure 23b. output sink current vs. supply voltage ty p. -12 -10 -8 -6 -4 -2 0 10 12 14 16 18 20 v bs floating supply voltage (v) v s offset supply voltage (v ) figure 24. maxim um v s negative offset vs. supply voltage ty p.
irs21952spbf 15 notes: 1. dimensioning & tolerancing per ansi y14.5w-1982 2. controlling dimension. millimeter 3. dimensions are shown in millimeter [inches] 4. outline conforms to jedec outline ms-012ac 5. dimension is the length of lead for soldering to a substrate 6. dimension does not include mold protusions. mold protusions shall not exceed 0.15 [.006] 16-lead soic (narrow body)
irs21952spbf 16 carrier tape dimension for 16soicn code min max min max a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 15.70 16.30 0.618 0.641 d 7.40 7.60 0.291 0.299 e 6.40 6.60 0.252 0.260 f 10.20 10.40 0.402 0.409 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 16soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 22.40 n/a 0.881 g 18.50 21.10 0.728 0.830 h 16.40 18.40 0.645 0.724 metric imperial e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c
irs21952spbf 17 so-16n package is msl2 qualified. this product has been designed and qualified for the industrial level. qualification standards can be found at ir?s web site http://www.irf.com/ world headquarters: 233 kansas st., el segundo, ca lifornia 90245 tel: (310) 252-7105 data and specifications subject to ch ange without notice 06/22/2007 order information 16-lead soic irs21952spbf 16-lead soic tape & reel irs21952strpbf

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